1. Field of the Invention
The present invention generally relates to the design of integrated circuit structures and more specifically to an improved method for checking integrated circuit designs against various parameters.
2. Description of the Related Art
As the minimum feature size in semiconductor integrated circuit (IC) technology is pushed near or below the wavelength of the light used in microlithographic projection printing, diffraction effects introduce significant differences between the patterns used on microlithographic reticles and the resulting printed structures on a semiconductor wafer. Similarly, the smaller the circuit elements become, the more difficult it is to create the desired pattern shapes on the wafer due to factors such as localized etch variations, mask distortions, lens distortions, topography variations, and nonuniform material composition. These dimensional variations can cause unacceptable deviations in device and interconnect characteristics, which in turn can degrade circuit performance and accuracy. The magnitude of this problem increases as critical circuit dimensions decrease.
A principle cause of these dimensional variations in a given structure is the degree of proximity to nearby shapes. Conventional solutions address this problem by changing (e.g., compensating) the dimensions of shapes in the mask design. However, in conventional practice, these corrections are performed after the entire design is completed. At this point in the design, there may not be sufficient flexibility to make all desirable compensations. As described in detail below, with the invention the compensations are made earlier in the design process, thereby greatly improving the overall circuit design and performance.
It is, therefore, an object of the present invention to provide a structure and method of designing an integrated circuit that includes generating at least one device shape, altering the device shape to comply with predetermined rules, forming a first hierarchical level abstraction around the device shape (where the first hierarchical level abstraction represents a perimeter of the device shape), preparing a first hierarchical level arrangement of first hierarchical level abstractions, altering the first hierarchical level arrangement to comply with the predetermined rules, forming a second hierarchical level abstraction around the first hierarchical level arrangement (where the second hierarchical level abstraction represents a perimeter of the first hierarchical level arrangement), preparing a second hierarchical level arrangement of second hierarchical level abstractions, and altering the second hierarchical level arrangement to comply with the predetermined rules.
The altering of the first hierarchical level includes comparing the first hierarchical abstractions with each other for consistency with the predetermined rules and the altering of the second hierarchical level includes comparing the second hierarchical abstractions with each other for consistency with the predetermined rules.
The method also includes, for each successive hierarchical level, forming a next hierarchical level abstraction around a previous hierarchical level arrangement, the next hierarchical level abstraction representing a perimeter of the previous hierarchical level arrangement, preparing a next hierarchical level arrangement of a plurality of next hierarchical level abstractions, and altering the next hierarchical level arrangement to comply with the predetermined rules.
The predetermined rules include spacing requirements, uniform element formation requirements, uniform material thickness requirements, width, alignment, step, coverage, minimum necking, etc. The altering of the device shape includes making shape corrections to nullify anticipated manufacturing effects.
The invention reduces across chip line variation (ACLV) that arises from proximity process effects which cause variations in printing for nested or isolated structures in microchip fabrication. The invention is particularly useful for logic parts that include many different local circuit blocks. The invention takes available models for predicting the printability of microchip circuit features and directly incorporates them within a microchip circuit design methodology to produce overall improved circuit performance.